对接口进行ESD保护的实现方案

　　The reasons these structures are insufficient are twofold: They are too small to absorb large energy transients that interfaces commonly experience in the field, and they reside too far away from the interface-entry point to prevent coupling to adjacent traces. Once an I/O line’s on-chip-ESD cell begins to conduct, a current transient develops along its trace, exciting the trace’s inductance, causing a corresponding voltage transient, Ldi/dt. Adjacent conductors with mutual inductance to the I/O trace see coupled transients that can exceed the capabilities on their own on-chip-ESD cells. These adjacent traces can include clock, data, or other nonported signals (Reference 2).

　　Mounting TVSs (transient-voltage suppressors) as close to the entry point as possible alleviates this problem by shunting the ESD event to ground before transient currents develop inside your product. Doing so can add substantially to your product’s robustness with minimal additional cost. “If a finger can get close to a node, protect it,” is a good rule of … errrrr … thumb. This rule applies to keypad switch lines, too, despite their insulating keycaps.

　　High-speed interfaces require TVSs with particularly low shunt capacitances. Check your vendor’s product line for devices built for specific high-speed interfaces. If you don’t find devices specifically for your interface, compare your signalin

g frequencies and source-and-line c磁环电感haracteristics with those of interface standards that the vendor explicitly supports. When considering TVS manufacturers’ claims, be sure to understand which ESD source model they use when specifying their devices. The JEDEC HBM (human-body model), for example, uses a 100-pF capacitor discharging through a 1.5-kΩ resistor. The repeatability of the test method’s results has been historically an area of concern (Reference 3). The 贴片功率电感器生产厂IEC-61000-4-2 standard’s test method promotes repeatability, and its source model—150-pF behind 150Ω—is more demanding of your design.

　　References

　　Sicard, Etienne and Syed Mahfuzul Aziz, “Application note on 45-nm technology,” Institut National des Sciences Appliquées de Toulouse, June 27, 2007.

　　“Disadvantage of on-chip transient protection,” Application Note SI97-04, Semtech, September 2000.

　　Verhaege, Koen, et al, “Recommendations to further improvements of HBM ESD component level test specifications,” Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium, September 1996.

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