Cypress CY3275可编程低压动力线通信开发方案

Cypress公司的CY3275是采用CY8CPLC20 PSoC的可编程低压动力线通信开发套件,用于低带宽的动力线通信.CY3275能进行系统设计,在低压(12-24V AC/DC)动力线上发送数据高达2400 bps.本文介绍了CY8CPLC20主要特性,PSoC核方框图,PLC 解决方案框图,两个节点的PLC 系统级方框图以及CY3275可编低压PLC开发套件主要特性,电路图,材料厂清单和PCB元件布局图.

CY8CPLC20: Powerline Communication Solution

The CY8CPLC20 is an integrated powerline communication (PLC) chip with the powerline modem PHY and network protocol stack running on the same device. Apart from the PLC core, the CY8CPLC20 also offers Cypress’s revolutionary PSoC technology that enables system designers to integrate multiple functions on the same chip.

CY8CPLC20主要特性:

■ Powerline communication solution

❐ Integrated powerline modem PHY

❐ Frequency shift keying modulation

❐ Configurable baud rates up to 2400 bps

❐ Powerline optimized network protocol

❐ Integrates data link, transport, and network layers

❐ Supports bidirectional half duplex communication

❐ 8-bit CRC error detection to minimize data loss

❐ I2C enabled powerline application layer

❐ Supports I2C frequencies of 50, 100, and 400 kHz

❐ Reference designs for 110 V/240 V AC and 12 V/24 V AC/DC Powerlines

❐ Reference designs comply with CENELEC EN 50065-1:2001 and FCC Part 15

■ Powerful Harvard-architecture Processor

❐ M8C processor speeds to 24 MHz

❐ Two 8x8 multiply, 32-bit accumulate

■ Programmable system resources (PSoC® Blocks)

❐ 12 Rail-to-Rail Analog PSoC Blocks provide:

• Up to 14-bit ADCs

• Up to 9-bit DACs

• Programmable gain amplifiers

• Programmable filters and comparators

❐ 16 Digital PSoC Blocks provide:

• 8 to 32-bit Timers, Counters, and PWMs

• CRC and PRS Modules

• Up to four full duplex UARTs

• Multiple SPI™ masters or slaves

• Connectable to all GPIO Pins

❐ Complex peripherals by combining blocks

■ Flexible on-chip memory

❐ 32 KB flash program storage 50,000 erase or write cycles

❐ 2 KB SRAM data storage

❐ EEPROM emulation in flash

■ Programmable pin configurations

❐ 25 mA sink, 10 mA source on all GPIOs

❐ Pull-up, Pull-down, high Z, strong, or open drain drive Modes on all GPIO

❐ Up to 12 analog inputs on all GPIOs

❐ Configurable interrupt on all GPIOs

■ Additional system resources

❐ I2C slave, master, and multi-master to 400 kHz

❐ Watchdog and sleep timers

❐ User-configurable low-voltage detection

❐ Integrated supervisory circuit

❐ On-chip precision voltage reference

■ Complete development tools

❐ Free development software (PSoC Designer™)

❐ Full-featured in-circuit emulator (ICE) and programmer

❐ Full-speed emulation

❐ Complex breakpoint structure

❐ 128 KB trace memory

❐ Complex events

❐ C Compilers, assembler, and linker

图1.Cypress PLC 解决方案框图

图2.CY8CPLC20 PSoC核框图

CY3275可编低压PLC开发套件

Cypress’s Powerline Communication (PLC) solution makes it possible to transmit command and control data over high-voltage and low-voltage powerlines. This solution is developed for low bandwidth powerline communication.

The CY3275 Programmable Low Voltage Powerline Communication Development Kit is a tool to do system design using the ability of the CY8CPLC20 devices to transmit data up to 2400 bps over Low Voltage (12-24V AC/DC) Powerlines.

CY3275可编低压PLC开发套件主要特性:

User friendly PLC Control Panel application available on the kit CD-ROM

Chip power supply derived from 12V to 24V AC/DC

CY8CPLC20-OCD chip -- 100-pin TQFP on chip debug (OCD) device that allows for the quick design and debug of PLC applications

User configurable general purpose LEDs

General purpose 8-bit DIP switch

RJ45 connector to use ICE debugger

RS232 COM port for communication

Header to attach LCD card

I2C header for communicating to external devices

ISSP header for programming the CY8CPLC20 chip

CY3275可编低压PLC开发套件包括:

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H桥PMOS管发热


自己画的一个电路，用来控制制冷片工作用的。


现在我通过PWM控制电压让制冷片工作的时候，IO3给高，IO4给低，电流从左侧臂流向右侧臂，Q2和Q5发热发的很严重，Q14不会，是VGS没

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